The present invention relates to photo-sensors and more particularly, to photo-sensors effectively applied to cameras and the like.
The auto-focusing (AF) systems of cameras are roughly classified into two types, i.e., passive and active types. In the former type, the scene to be picked up is passed through two lenses (or separator lenses) to obtain two images for sensing with respective sensors, and distance measurement is performed from the distance between the two sensed images. In the latter type, a light beam is projected from an LED in a camera body or the like onto the scene, and distance measurement is performed by detecting the position of the reflected light beam. The former type systems have a problem that the accuracy of the distance measurement is reduced when the contrast of the scene is low. The latter type systems have a problem that it is impossible to detect the light projected form the LED when the background of the scene is bright. Both type systems thus have their own merits and demerits.
In the presence of these problems, Japanese Patent Laid-Open No. 64-18255 discloses a line sensor for the active AF system which permits expanding the imaging scene capable of AF by removing background light. FIG. 9 shows the construction of one pixel of the disclosed line sensor, and FIG. 10 outlines an active AF module.
Referring to FIG. 9, a photo-sensor cell 101 is shown, which includes a MOS transistor FT6 and a p-channel and an n-channel MOS transistor FT10 and FT11. The MOS transistor FT6 has its drain D6 connected to the drain D10 of the MOS transistor FT10. The MOS transistor FT10 has its source S10 held at a reference potential Vref and its gate G10 connected to one terminal of a capacitor 107 as shown. The MOS transistor FT11 is connected to the drain D6 of the MOS transistor FT6 as shown. The MOS transistor FT11 serves to turn on and off the gate G10 and the drain D10 of the MOS transistor FT10 according to a switching signal SW applied to its gate G11. In the application of a solid-state imager having the photo-sensor cell 101 to a light-receiving element 124 as shown in FIG. 10, before the measurement of the distance of a scene 122 the charge corresponding to photo-current ISHO, which is generated in a photo-diode 102 by the light other than the signal light, i.e., background light, is stored in the capacitor 107.
As shown in FIG. 9, the photo-diode 102 is connected to one terminal of a MOS transistor FT0 having the other terminal connected to one terminal of a switching transistor T1. The switching transistor FT1 is connected to one terminal of a capacitor 105, and its switching operation is brought about with a data accumulation signal DT applied to its gate G1. The capacitor 105 is connected to a switching element FT3, and its terminal voltage V0 is initialized to the reference potential Vref by turning on the switching element FT3 with a reset signal RST applied to the gate G3 of the element FT3. In the circuit construction shown in FIG. 9, transistors FT4 and FT5, a constant current source 103 including transistors FT7 and FT8 and the capacitor 105 constitutes a circuit for outputting the signal detected by the above circuit construction. That is, an output corresponding to the terminal voltage V0 across the capacitor 105 is outputted to a video line 104 in a manner as will be described hereinunder.
For storing background light in the above circuit, prior to the distance measurement the photo-diode 102 and the capacitor 105 are held disconnected from each other without supplying the data accumulation signal DT to the gate G1 of the switching transistor FT1. Also, the terminal voltage V0 across the capacitor 105 is initialized to the reference potential Vref by applying the reset signal RST to the gate G3 of the switching transistor FT3 as noted above. Furthermore, the light source 120, i.e., the LED, is not driven, so that no signal light is incident on the photo-diode 102 but the sole background light is incident on the light-receiving element 124. Still further, the switching signal SW is held to be at a high level to hold the MOS transistor FT11 xe2x80x9cONxe2x80x9d. In this state, the MOS transistor FT10 functions as a load having a predetermined resistance, and the photo-current ISHO generated in the photo-diode 102 by the background light, is supplied from the reference potential Vref to flow through the MOS transistor FT10 and the transistor FT6 into the photo-diode 102.
As stated before, the photo-diode 102 and the capacitor 105 are held disconnected at this time. Thus, the flow of the photo-current ISHO due to the background light causes the terminal voltage across the capacitor 107 to become lower than the reference potential Vref in correspondence to the resistance of the MOS transistor FT10 functioning as the load. In other words, the charge corresponding to the photo-current ISHO due to the background light is accumulated in the capacitor 107.
As the charge is accumulated in the capacitor 107, it is eventually saturated. Thus, the saturated accumulation charge caused by the photo-current ISHO due to the background light can be stored in the capacitor 107. That is, the photo-current ISHO can be stored as the voltage at the gate G10 of the MOS transistor FT10.
In this state, signal accumulation of pixel data as signal light in the capacitor 105 can be started. Specifically, at this time the light source 120 is driven to let signal light be incident on the light-receiving element 124, i.e., the photo-diode 102, while at the same time the data accumulation signal DT is applied to the gate G1 of the switching transistor FT1 to turn on this transistor and connect the capacitor 105 and the photo-diode 102 to each other.
Although background light is incident on the photo-diode 102 at this time in superimposition on the signal light, since the photo-current ISH0 due to the background light flows on the basis of the voltage stored at the gate G10 of the MOS transistor FT10, only photo-current ISHxe2x80x2 due to the signal light flows from the capacitor 105 to the photo-diode 102.
Thus, the terminal voltage V0 across the capacitor 105 is reduced from the initial level Vref according to the sole photo-current ISHxe2x80x2 due to the signal light. It is thus possible to obtain a voltage change corresponding to the sole signal light intensity, that is, detect a signal free from the influence of the background light.
By turning on the switching element FT5, which is connected to the transistor FT4 and the current amplifier constituted by the constant current source 103 including the transistors FT7 and FT8, i.e., a source follower, the accumulated terminal voltage V0 across the capacitor 105 is read out through the switching element FT5 to a video line 104.
Photo-sensor cells as described above are arranged one- or two-dimensionally to form a line or an area sensor. The line sensor described in the disclosure noted above is summarized as follows. The MOS transistors FT10 and FT11 and the capacitor 107 constitute a current memory to store photo-current ISHO due to background light. In addition, the switching transistor FT1, the transistor FT3 and the capacitor 105 constitute a photo-current sensor for sensing signal light. Thus, the sole photo-charge corresponding to the light projected from the light source is accumulated and read out to reduce the adverse effects of the background light.
The line sensor shown in FIG. 9, however, has the following drawback. Denoting the voltage applied to the gate of the MOS transistor FT6 by VG, the gate-source voltage across this transistor by VGS6 and the gate-source voltage across the MOS transistor FT0 by VGSO, when the data accumulation signal DT is xe2x80x9cOFFxe2x80x9d, that is, when storing the background light in the capacitor 107, the terminal voltage VPD across the photo-diode 102 is given as:
VPD=VGxe2x88x92VGS6(ISHO)xe2x80x83xe2x80x83(1)
At this time, since the MOS transistor FT0 is xe2x80x9coffxe2x80x9d, VPD corresponds to ISHO.
When the data accumulation data DT is turned on denoting the voltage applied to the gate of the MOS transistor FT0 by VG, the terminal voltage VPD across the photo-diode 102 is expressed in the following two ways.
VPD=VGxe2x88x92VGS6(ISHO)
and VPSD=VGxe2x88x92VGS0(ISHOxe2x80x2)xe2x80x83xe2x80x83(2)
As shown, the terminal voltage VPD across the photo-diode 102 is determined on the basis of the influence of both the gate-grounded MOS transistors FT6 and FT0, and a feed-back is provided such that VGS6=VGS0. For example, the feed-back has an effect of increasing the drain voltage at the MOS transistors FT0 and FT6 and reducing the source-drain voltage across the MOS transistor FT10, thus making the current ISH0 flowing out from the current memory to be lower than the stored level. In the long run, ISH0=ISHxe2x80x2 is provided by the feed-back, so that the charge accumulation in the capacitor 105 will include other influence than that by the background light. In other words, with the line sensor of the structure as shown in FIG. 9 no great improvement with respect to the background light can be expected.
The inventor accordingly has proposed a solid-state imager capable of solving the above problem in Japanese Patent Laid-Open No. 7-203319. FIG. 11 shows an example of the disclosed structure.
Referring to FIG. 11, a transistor 1 has its source connected to a photo-diode 2 and its drain connected to a charge accumulation capacitor 5. An inverter 12 which includes a source-grounded amplifying transistor 10 and a load transistor 11 serving as a load of the transistor 10 and having the gate held at a fixed potential VBIAS1, provides an output fed to the gate of the transistor 1. The input side of the inverter 12, i.e., the gate of the source-grounded p-MOS transistor 10, is connected to the photo-diode 2. The inverter 2 and the transistor 1 form together a feed-back loop, and the photo-diode 2 is substantially held in a low impedance state. Thus, the potential at the photo-diode 2 serves as a constant bias, and photo-charge generated in the photo-diode 2 steadily flows through the transistor 1 to the charge accumulation capacitor 5 irrespective of its magnitude.
A current memory 13 which includes a current memory transistor 6, a current memory capacitor 7 and a switching transistor 8 having the gate to which a control pulse signal "PHgr"MC for controlling the sampling and holding of the current to be stored, is connected in parallel with the charge accumulation capacitor 5. An amplifier 14 is provided to amplify the voltage across the capacitor 5. Although only a single one is shown, a plurality of selection transistors 9 which each have the gate connected to a shift register 3 for selectively outputting the output of each of the amplifiers 14 which each correspond to each pixel (not shown), are each provided between each amplifier and the video line.
The operation of the solid-state imager having the above construction will now be described. The pixels of the solid-state imager are each operated as follows to read out a signal corresponding to the light projected from the light source while removing the background light.
When the control pulse "PHgr"MC is turned on in the absence of light projected from the light source, photo-current IPD generated due to the background light in th e photo-diode 2 entirely flows into the current memory transistor 6, and thus we have IPD=IM. At this time, the potential at the node N1, i.e., at the charge accumulation capacitor 5, is constituted by the source-gate voltage VGS of the current memory transistor 6 corresponding to IM.
A state when the switching transistor 8 is subsequently turned off will now be considered. Even in this state, IPD=IM if feed-through charge of the transistor 8 is ignored. At this time, the node N1 assumes a floating state and held at VGS. By causing the light projection from the light source in this state, in each pixel receiving the reflected light photo-current IPDxe2x80x2 due to the light projection to IPD to obtain IPD+IPDxe2x80x2. Consequently, sole charge corresponding to the photo-current IPDxe2x80x2 due to the light projection is accumulated in the charge accumulation capacitor 5.
After the end of the light projection, the charge accumulation signal is read out of each capacitor 5 through each amplifier 14 to the video line 4 by successively turning on the selection transistors 9. By reading out the outputs of all the pixels in this way, it is possible to detect the position of the light-receiving element, at which the reflected light corresponding to the projected light is incident.
With the construction as described, the problem posed in the case of the structure shown in FIG. 9 can be solved to obtain sensing of the projected light while effectively removing the background light. As a result of investigations, however, the following problems were found.
(1) With accumulation of the photo-current IPDxe2x80x2 due to the light projection in the charge accumulation capacitor 5, the voltage at the node N1 is changed, causing changes in the source-drain voltage across the transistor 6 generating the memory current IM and thus deviation of the level of the memory current IM from the stored level. This means that when the photo-current IPD due to the background light, i.e., the memory current IM, is high compared to the photo-current IPDxe2x80x2 doe to the light projection, the deviation of the memory current IM corresponding to the photo-current IPDxe2x80x2 due to the light projection has great effects, making it impossible to obtain accurate measurement of the photo-current IPDxe2x80x2 due to the light projection.
(2) The photo-current IPD due to the background light causes changes in the conductance of the transistor 1, and the frequency band of the first stage circuit constituted by the inverter 12 and the transistor 1 is changed in dependence on the photo-current. Particularly, when the photo-current IPD due to the background light is low, the conductance is extremely reduced, making it difficult to increase the frequency band of the circuit again.
The present invention was proposed in view of the above problems, and it has an object of providing a photo-sensor capable of accurate removal of photo-current due to background light when sensing the photo-current due to light projection, and in which the frequency band of the photo-current sensing system is independent of photo-diode current.
According to a first aspect of the present invention, there is provided a photo-sensor comprising a photo-electric converting element, a transistor having the source connected to the photo-electric converting element for passing photo-current generated in the photo-electric converter, an inverting amplifier having the input side connected to the juncture between the photo-electric converting element and the transistor for amplifying the output signal from the photo-electric converting element, a signal storing circuit provided between the source and the gate of the transistor for storing a signal corresponding to the photo-current, and a switching element provided between the output side of the inverting amplifier and the gate of the transistor.
In the photo-sensor according,
the switching element executes a switching operation in correspondence to the timing of storing the output signal from the photo-electric converting element in the signal storing circuit;
the signal storing circuit contains a gate capacitance of the transistor;
the signal storing circuit contains the gate capacitance of the transistor that is determined by the size of the gate area of the transistor;
a signal accumulation capacitor and a switching element for resetting the signal accumulation capacitor are provided between the input and output sides of the inverting amplifier;
a resistor and a switching element in series with the resistor are provided between the input and output sides of the inverting amplifier, and
the output side of the inverting amplifier is connected to the output side of a second stage inverting amplifier, and a signal accumulation capacitor and a switching element for resetting the signal accumulation capacitor are provided between the input and output sides of the second stage inverting amplifier.
Other objects and features will be clarified from the following description with reference to attached drawings.